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Section 6 Exception Handling
R01UH0134EJ0400 Rev. 4.00 Page 145 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
6.5.2 Interrupt Priority Level
The interrupt priority order is predetermined. When multiple interrupts occur simultaneously
(overlap), the interrupt controller determines their relative priorities and starts exception handling
according to the results.
The priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest
and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is
always accepted. The priority level of user debugging interface interrupts is 15. Priority levels of
IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts can be set freely using
the interrupt priority registers 01, 02, and 05 to 22 (IPR01, IPR02, and IPR05 to IPR22) of the
interrupt controller as shown in table 6.9. The priority levels that can be set are 0 to 15. Level 16
cannot be set. See section 7.3.1, Interrupt Priority Registers 01, 02, 05 to 22 (IPR01, IPR02, IPR05
to IPR22), for details of IPR01, IPR02, and IPR05 to IPR22.
Table 6.9 Interrupt Priority Order
Type Priority Level Comment
NMI 16 Fixed priority level. Cannot be masked.
User debugging interface 15 Fixed priority level.
IRQ 0 to 15 Set with interrupt priority registers 01, 02, and 05
to 22 (IPR01, IPR02, and IPR05 to IPR22).
PINT
On-chip peripheral module