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Section 15 Serial Communication Interface with FIFO
Page 770 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
15.5 Interrupts
This module has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI),
receive FIFO data full (RXI), and break (BRI).
Table 15.12 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register
(SCFSR) is set to 1, a TXI interrupt request is generated. The direct memory access controller can
be activated and data transfer performed by this TXI interrupt request. At this time, an interrupt
request is not sent to the CPU.
When an RXI request is enabled by the RIE bit and the RDF flag or the DR flag in SCFSR is set
to 1, an RXI interrupt request is generated. The direct memory access controller can be activated
and data transfer performed by this RXI interrupt request. At this time, an interrupt request is not
sent to the CPU. The RXI interrupt request caused by the DR flag is generated only in
asynchronous mode.
It is possible to generate only the ERI or BRI interrupt without generating the RXI interrupt by
setting the RIE bit to 0 and the REIE bit to 1 in SCSCR.
The TXI indicates that transmit data can be written, and the RXI indicates that there is receive data
in SCFRDR.
Table 15.12 Interrupt Sources
Interrupt
Source
Description
Direct Memory
Access
Controller
Activation
Priority on
Reset Release
BRI Interrupt initiated by break (BRK) or overrun error
(ORER)
Not possible High
ERI Interrupt initiated by receive error (ER) Not possible
RXI Interrupt initiated by receive FIFO data full (RDF) or
data ready (DR)
Possible
TXI Interrupt initiated by transmit FIFO data empty
(TDFE)
Possible
Low