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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 311 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 9.10 Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (2)-2
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits) 01 (12 bits) 10 (10 bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
SDRAM Pin Function
A17 A27 A17 Unused
A16 A26 A16
A15 A25 A15
A14 A24*
2
A24*
2
A13 (BA1) Specifies bank
A13 A23*
2
A23*
2
A12 (BA0)
A12 A22 A12 A11 Address
A11 A21 L/H*
1
A10/AP Specifies
address/precharge
A10 A20 A10 A9 Address
A9 A19 A9 A8
A8 A18 A8 A7
A7 A17 A7 A6
A6 A16 A6 A5
A5 A15 A5 A4
A4 A14 A4 A3
A3 A13 A3 A2
A2 A12 A2 A1
A1 A11 A1 A0
A0 A10 A0 Unused
Example of connected memory
256-Mbit product (4 Mwords 16 bits 4 banks, column 10 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification