Filter
Top Products
Section 25 NAND Flash Memory Controller
Page 1296 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
11, 10 ACM[1:0] 00 R/W Access Mode Specification 1 and 0
Specify access mode.
00: Command access mode
01: Sector access mode
10: Setting prohibited
11: Setting prohibited
9 NANDWF 0 R/W NAND Wait Insertion Operation
0: Performs address or data input/output in one FCLK
cycle
1: Performs address or data input/output in two FCLK
cycles
8 to 4 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
3 CE 0 R/W Chip Enable
0: Disables the chip (Outputs high level to the FCE pin)
1: Enables the chip (Outputs low level to the FCE pin)
2, 1 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
0 1 R Reserved
This bit is always read as 1. The write value should
always be 1.