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Section 19 Serial I/O with FIFO
Page 962 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
19.3.10 Receive Data Assign Register (SIRDAR)
SIRDAR specifies the position of the receive data in a frame (slot number).
Bit:
Initial Value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
R/W R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W
RDLE
- - - RDLA3 RDLA2 RDLA1 RDLA0 RDRE - - - RDRA3 RDRA2 RDRA1 RDRA0
Bit Bit Name
Initial
Value R/W Description
15 RDLE 0 R/W Receive Left-Channel Data Enable
0: Disables left-channel data reception
1: Enables left-channel data reception
14 to 12 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
11
10
9
8
RDLA3
RDLA2
RDLA1
RDLA0
0
0
0
0
R/W
R/W
R/W
R/W
Receive Left-Channel Data Assigns 3 to 0
Specify the position of left-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
Receive data for the left channel is stored in the
SIRDL bit in SIRDR.
7 RDRE 0 R/W Receive Right-Channel Data Enable
0: Disables right-channel data reception
1: Enables right-channel data reception
6 to 4 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
3
2
1
0
RDRA3
RDRA2
RDRA1
RDRA0
0
0
0
0
R/W
R/W
R/W
R/W
Receive Right-Channel Data Assigns 3 to 0
Specify the position of right-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
Receive data for the right channel is stored in the
SIRDR bit in SIRDR.