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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1525 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(c) Status Stage
Zero-length packet data transfers are done in the direction opposite to that in the data stage. As
with the data stage, data transfers are done using the DCP buffer memory. Transactions are done
in the same manner as the data stage.
For the data packets of the status stage, the data PID must be transferred as DATA1. The data PID
should be set to DATA1 using the SQSET bit in DCPCTR.
For reception of a zero-length packet, the received data length must be confirmed using the DTLN
bits in CFIFOCTR after the BRDY interrupt is generated, and the buffer memory must then be
cleared using the BCLR bit.
(2) Control Transfers when the Function Controller Function is Selected
(a) Setup Stage
This module always sends an ACK response in response to a setup packet that is normal with
respect to this module. The operation of this module operates in the setup stage is noted below.
(i) When a new USB request is received, this module sets the following registers:
Set the VALID bit in INTSTS0 to 1.
Set the PID bit in DCPCTR to NAK.
Set the CCPL bit in DCPCTR to 0.
(ii) When a data packet is received right after the SETUP packet, the USB request parameters are
stored in USBREQ, USBVAL, USBINDX, and USBLENG.
Response processing with respect to the control transfer should always be carried out after first
setting VALID = 0. In the VALID = 1 state, PID = BUF cannot be set, and the data stage cannot
be terminated.
Using the function of the VALID bit, this module is able to interrupt the processing of a request
currently being processed if a new USB request is received during a control transfer, and can send
a response in response to the newest request.
Also, this module automatically judges the direction bit (bit 8 of the bmRequestType) and the
request data length (wLength) of the USB request that was received, and then distinguishes
between control read transfers, control write transfers, and no-data control transfers, and controls
the stage transition. For a wrong sequence, the sequence error of the control transfer stage
transition interrupt is generated, and the software is notified. For information on the stage control
of this module, see figure 26.7.