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Section 8 Cache
R01UH0134EJ0400 Rev. 4.00 Page 209 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Section 8 Cache
8.1 Features
Capacity
Instruction cache: 8 Kbytes
Operand cache: 8 Kbytes
Structure: Instructions/data separated, 4-way set associative
Way lock function (only for operand cache): Way 2 and way 3 are lockable
Line size: 16 bytes
Number of entries: 128 entries/way
Write system: Write-back/write-through selectable
Replacement method: Least-recently-used (LRU) algorithm
8.1.1 Cache Structure
The cache separates data and instructions and uses a 4-way set associative system. It is composed
of four ways (banks), each of which is divided into an address section and a data section.
In each way, each of the address and data sections is divided into 128 entries. The data section of
the entry is called a line. Each line consists of 16 bytes (4 bytes 4). The data capacity per way is
2 Kbytes (16 bytes 128 entries), with a total of 8 Kbytes in the cache as a whole (4 ways).
Figure 8.1 shows the operand cache structure. The instruction cache structure is the same as the
operand cache structure except for not having the U bit.