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Section 16 Renesas Serial Peripheral Interface
Page 828 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
On operation A shown in table 16.7, this module does not detect an error. Whether SPDR can be
written to or not can be checked using the T[3:0] bits in the buffer data count setting register
(SPBFDR).
Likewise, this module does not detect an error on operation B. In a serial transfer that was started
before the shift register was updated, this module sends the data that was received in the previous
serial transfer, and does not treat the operation indicated in B as an error. Note that the received
data from the previous serial transfer is retained in the receive buffer of SPDR, thus it can be
correctly read.
Similarly, this module does not detect an error on operation C. To prevent extraneous data from
being read, the number of receive data units stored in the receive buffer should be read from the
R[5:0] bits in the buffer data count setting register (SPBFDR).
An overrun error shown in D is described in section 16.4.6 (1), Overrun Error. A mode fault error
shown in E is described in section 16.4.6 (2), Mode Fault Error.