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Section 33 Power-Down Modes
R01UH0134EJ0400 Rev. 4.00 Page 1785 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
3 1 R Reserved
This bit is always read as 1. The write value should
always be 1.
2 MSTP72 1 R/W Module Stop 72
When the MSTP72 bit is set to 1, the clock supply to
the compare match timer is halted.
0: The compare match timer runs.
1: Clock supply to the compare match timer is halted.
1 1 R Reserved
This bit is always read as 1. The write value should
always be 1.
0 MSTP70 1 R/W Module Stop 70
When the MSTP70 bit is set to 1, the clock supply to
the NAND flash memory controller is halted.
0: The NAND flash memory controller runs.
1: Clock supply to the NAND flash memory controller
is halted.