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R01UH0134EJ0400 Rev. 4.00 Page xxiii of xl
Sep 24, 2014
17.4.2 Master Transmit Operation ............................................................................... 869
17.4.3 Master Receive Operation ................................................................................. 871
17.4.4 Slave Transmit Operation ................................................................................. 873
17.4.5 Slave Receive Operation ................................................................................... 876
17.4.6 Clocked Synchronous Serial Format ................................................................. 877
17.4.7 Noise Filter ....................................................................................................... 881
17.4.8 Example of Use ................................................................................................. 882
17.5 Interrupt Requests ............................................................................................................. 886
17.6 Bit Synchronous Circuit .................................................................................................... 887
17.7 Usage Notes ...................................................................................................................... 890
17.7.1 Note on Setting for Multi-Master Operation ..................................................... 890
17.7.2 Note on Master Receive Mode .......................................................................... 890
17.7.3 Note on Setting ACKBT in Master Receive Mode ........................................... 890
17.7.4 Note on the States of Bits MST and TRN when Arbitration is Lost ................. 891
17.7.5 Note on I
2
C-bus Interface Master Receive Mode .............................................. 891
17.7.6 Note on IICRST and BBSY bits ....................................................................... 891
17.7.7 Note on Issuance of Stop Conditions in Master Transmit Mode while
ACKE = 1 ......................................................................................................... 891
Section 18 Serial Sound Interface ...................................................................... 893
18.1 Features ............................................................................................................................. 893
18.2 Input/Output Pins .............................................................................................................. 896
18.3 Register Description ......................................................................................................... 897
18.3.1 Control Register (SSICR) ................................................................................. 899
18.3.2 Status Register (SSISR) .................................................................................... 906
18.3.3 Transmit Data Register (SSITDR) .................................................................... 910
18.3.4 Receive Data Register (SSIRDR) ..................................................................... 910
18.3.5 FIFO Control Register (SSIFCR) ..................................................................... 911
18.3.6 FIFO Status Register (SSIFSR) ........................................................................ 914
18.3.7 Transmit FIFO Data Register (SSIFTDR) ........................................................ 917
18.3.8 Receive FIFO Data Register (SSIFRDR) ......................................................... 917
18.4 Operation Description ....................................................................................................... 918
18.4.1 Bus Format ........................................................................................................ 918
18.4.2 Non-Compressed Modes ................................................................................... 919
18.4.3 Operation Modes ............................................................................................... 929
18.4.4 Transmit Operation ........................................................................................... 930
18.4.5 Receive Operation ............................................................................................. 933
18.4.6 Serial Bit Clock Control .................................................................................... 936
18.5 Usage Notes ...................................................................................................................... 937
18.5.1 Limitations from Underflow or Overflow during DMA Operation .................. 937