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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 231 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Figure 9.1 shows a block diagram of this module.
CMNCR
CS0WCR
CS6WCR
CS0BCR
CS6BCR
SDCR
RTCSR
RTCNT
RTCOR
Comparator
Bus
mastership
controller
Wait
controller
Area
controller
Internal bus
Memory
controller
Refresh
controller
[Legend]
Module bus
BSC
CS0 to CS6
WAIT
A25 to A0,
D15 to D0,
BACK
BREQ
Bus use enable for
NAND flash memory controller
Bus request from
NAND flash memory controller
BS, RD/WR,
RD, WE1, WE0,
RAS, CAS,
CKE, DQMU, DQML,
AH, IOIS16,
CE2A, CE2B
CMNCR
CSnWCR
CSnBCR
SDCR
RTCSR
RTCNT
RTCOR
: Common control register
: CSn space wait control register (n =0 to 6)
: CSn space bus control register (n = 0 to 6)
: SDRAM control register
: Refresh timer control/status register
: Refresh timer counter
: Refresh time constant register
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Figure 9.1 Block Diagram of Bus State Controller