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Section 37 Electrical Characteristics
Page 2038 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
37.4.15 Video Display Controller 3 Timing
Table 37.21 Video Display Controller 3 Timing
Item Symbol Min. Typ. Max. Unit Figure
DV_CLK input clock
frequency
t
cyc 27 MHz Figure 37.71
DV_CLK input clock low
pulse width
tWIL 0.4 tcyc
DV_CLK input clock high
pulse width
tWIH 0.4
LCD_EXTCLK input clock
frequency
tcyc 36 MHz
LCD_EXTCLK input clock
low pulse width
tWIL 0.4 tcyc
LCD_EXTCLK input clock
high pulse width
tWIH 0.4
LCD_CLK output clock
frequency
tcyc 36 MHz Figure 37.72
LCD_CLK output clock low
pulse width
tWIL 0.4 tcyc
LCD_CLK output clock high
pulse width
tWIH 0.4
Input data setup time tVS 10 ns Figure 37.73
Input data hold time tVH 3 ns
Output data delay time tDD 0 10 ns Figure 37.74
t
cyc
t
WL
t
WH
V
IH
1/2 PVcc
DV_CLK,
LCD_EXTCLK
V
IH
V
IL
V
IL
Figure 37.71 DV_CLK and LCD_EXTCLK Clock Input Timing