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Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00 Page 605 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
11.7.10 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 11.105 shows the timing in this case.
Input capture
signal
Write signal
Address
TCNT
TGR write cycle
T1
T2
M
TGR
M
TGR address
Pφ
Figure 11.105 Contention between TGR Write and Input Capture