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Section 9 Bus State Controller
Page 344 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
9.5.8 SRAM Interface with Byte Selection
The SRAM interface with byte selection is a memory interface that outputs the byte selection
signal (WEn) in both read and write bus cycles. This interface has 16-bit data pins and accesses
SRAMs having upper and lower byte selection pins, such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the SRAM
interface with byte selection is the same as that for the normal space interface. While in read
access of a byte-selection SRAM interface, the byte-selection signal is output from the WEn pin,
which is different from that for the normal space interface. The basic access timing is shown in
figure 9.34. In write access, data is written to the memory according to the timing of the byte-
selection pin (WEn). For details, please refer to the Data Sheet for the corresponding memory.
If the BAS bit in CSnWCR is set to 1, the WEn pin and RD/WR pin timings change. Figure 9.35
shows the basic access timing. In write access, data is written to the memory according to the
timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write
must be acquired by setting the HW1 and HW0 bits in CSnWCR. Figure 9.36 shows the access
timing when a software wait is specified.