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Section 28 Sampling Rate Converter
Page 1644 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
1, 0 IFTRG[1:0] 00 R/W Input FIFO Data Triggering Number
Specifies the condition in terms of the number on
which the IINT bit in the status register (SRCSTAT) is
set to 1. When the number of data units in the input
FIFO becomes equal to or smaller than the triggering
number listed below, the IINT bit is set to 1.
00: 0
01: 2
10: 4
11: 6