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Section 35 Motor Control PWM Timer
Page 1836 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
01 0 1
N
N–1
PWCNT
(lower 10 bits)
PWCYR
(lower 10 bits)
N–2
Compare matchCompare match
Figure 35.2 Cycle Register Compare Match
35.3.5 PWM Duty Registers_nA, nC, nE, nG (PWDTR_nA, PWDTR_nC, PWDTR_nE,
PWDTR_nG) (n = 1, 2)
There are four PWDTR_n registers (PWDTR_nA, PWDTR_nC, PWDTR_nE, and PWDTR_nG).
The PWDTR_nA is used for outputs PWMnA and PWMnB, PWDTR_nC for outputs PWMnC
and PWMnD, PWDTR_nE for outputs PWMnE and PWMnF, and PWDTR_nG for outputs
PWMnG and PWMnH.
PWDTR_n can not be directly accessed by the CPU. When a PWCYR_n compare match occurs,
data is transferred from the buffer register (PWBFR_n) to the duty register (PWDTR_n).
PWDTR_n is initialized to H'00 when the CST bit is cleared to 0.
15
—
—
—
14
—
—
—
13
—
—
—
12
OTS
0
—
11
—
—
—
8
DT8
0
—
10
—
—
—
9
DT9
0
—
Bit
Bit Name
Initial Value
R/W
7
DT7
0
—
6
DT6
0
—
5
DT5
0
—
4
DT4
0
—
3
DT3
0
—
0
DT0
0
—
2
DT2
0
—
1
DT1
0
—
Bit
Bit Name
Initial Value
R/W