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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 391 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
15, 14 DM[1:0] 00 R/W Destination Address Mode
These bits select whether the DMA destination
address is incremented, decremented, or left fixed. (In
single address mode, DM1 and DM0 bits are ignored
when data is transferred to an external device with
DACK.)
00: Fixed destination address
01: Destination address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longword-
unit transfer, +16 in 16-byte-unit transfer)
10: Destination address is decremented (–1 in byte-
unit transfer, –2 in word-unit transfer, –4 in
longword-unit transfer, setting prohibited in 16-
byte-unit transfer)
11: Setting prohibited
13, 12 SM[1:0] 00 R/W Source Address Mode
These bits select whether the DMA source address is
incremented, decremented, or left fixed. (In single
address mode, SM1 and SM0 bits are ignored when
data is transferred from an external device with
DACK.)
00: Fixed source address
01: Source address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longword-
unit transfer, +16 in 16-byte-unit transfer)
10: Source address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longword-
unit transfer, setting prohibited in 16-byte-unit
transfer)
11: Setting prohibited