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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1039 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit[15:0]: UMSR0 Description
0 [Clearing Condition] Writing '1' (initial value)
1 Unread received message is overwritten by a new message or overrun
condition
[Setting Condition]
When a new message is received before RXPR or RFPR is cleared
20.3.5 Timer Registers
The Timer is 16 bits and supports several source clocks. A pre-scale counter can be used to reduce
the speed of the clock. It also supports three Compare Match Registers (TCMR2, TCMR1,
TCMR0). The address map is as follows.
Important: These registers can only be accessed in Word size (16-bit).
Description Address Name Access Size (bits)
Timer Trigger Control Register 0 080 TTCR0 Word (16)
Cycle Maximum/Tx-Enable
Window Register
084 CMAX_TEW Word (16)
Reference Trigger Offset Register 086 RFTROFF Word (16)
Timer Status Register 088 TSR Word (16)
Cycle Counter Register 08A CCR Word (16)
Timer Counter Register 08C TCNTR Word (16)
Cycle Time Register 090 CYCTR Word (16)
Reference Mark Register 094 RFMK Word (16)
Timer Compare Match Register 0 098 TCMR0 Word (16)
Timer Compare Match Register 1 09C TCMR1 Word (16)
Timer Compare Match Register 2 0A0 TCMR2 Word (16)
Tx-Trigger Time Selection Register 0A4 TTTSEL Word (16)
Figure 20.12 Timer Registers