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Section 18 Serial Sound Interface
R01UH0134EJ0400 Rev. 4.00 Page 911 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
18.3.5 FIFO Control Register (SSIFCR)
The SSIFCR register specifies the data trigger counts of the transmit and receive FIFO data
registers, and enables or disables data resets and interrupt requests. SSIFCR can always be read or
written by the CPU.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bit:
Initial value:
R/W:
1514131211109876543210
Bit:
Initial value:
R/W:
000000 0000 000000
000000 00
RRRRRRRRRRRRRRRR
00000000
RRRRRRRRR/WR/WR/WR/WR/WR/WR/WR/W
---- ----- - ------
------- TIE- TFRSTRIETTRG[1:0] RTRG[1:0] RFRST
Bit Bit Name
Initial
Value R/W Description
31 to 8 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
7, 6 TTRG[1:0] 00 R/W Transmit Data Trigger Count
These bits specify the transmit data count (specified
transmit trigger count) at which the TDE flag in the
FIFO status register (SSIFSR) is set during
transmission.
The TDE flag is set to 1 when the transmit data count in
the transmit FIFO data register (SSIFTDR) is equal to
or less than the specified trigger count shown below.
00: 7 (1)*
01: 6 (2)*
10: 4 (4)*
11: 2 (6)*
Note: * The values in parenthesis are the number of
empty stages in SSIFTDR at which the TDE
flag is set.