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Section 9 Bus State Controller
Page 340 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
CKIO
A25 to A0
CSn
RD/WR
RAS
DQMx
D15 to D0
BS
Tpw
DACKn*
4
Tp Trr
A12/A11*
3
BA1*
1
BA0*
2
CAS
Notes: 1. Address pin to be connected to pin BA1 of SDRAM.
2. Address pin to be connected to pin BA0 of SDRAM.
3. Address pin to be connected to pin A10 of SDRAM.
4. The waveform for DACKn is when active low is specified.
Trc Trc Tmw
Hi-Z
TnopTrc Trr Trc
REF REF
MRS
Temw Tnop
EMRS
PALL
Figure 9.31 EMRS Command Issue Timing