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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 359 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
No. Condition Description Range Note
[7] Write data wait
cycles
During write access, a write cycle is
executed on the external bus only
after the write data becomes ready.
This write data wait period
generates idle cycles before the
write cycle. Note that when the
previous cycle is a write cycle and
the internal bus idle cycles are
shorter than the previous write
cycle, write data can be prepared in
parallel with the previous write cycle
and therefore, no idle cycle is
generated (write buffer effect).
0 or 1 For write write or write
read access cycles,
successive access cycles
without idle cycles are
frequently available due to
the write buffer effect
described in the left column.
If successive access cycles
without idle cycles are not
allowed, specify the minimum
number of idle cycles
between access cycles
through CSnBCR.
[8] Idle cycles
between
different
memory types
To ensure the minimum pulse width
on the signal-multiplexed pins, idle
cycles may be inserted before
access after memory types are
switched. For some memory types,
idle cycles are inserted even when
memory types are not switched.
0 to 2.5 The number of idle cycles
depends on the target
memory types. See table
9.19.