Filter
Top Products
Section 28 Sampling Rate Converter
Page 1658 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
28.3 Operation
28.3.1 Initial Setting
Figure 28.2 shows a sample flowchart for initial setting.
SRCCTRL
OVEN
IFS[3:0]
OFS
SRCIDCTRL IED
IEN
IFTRG[1:0]
SRCODCTRL OCH
OED
OEN
OFTRG[1:0]
Enabling/disabling of the OVF interrupt
Input sampling rate
CEEN
UDEN Enabling/disabling of the UDF interrupt
Output sampling rate
Input data endian
Enabling/disabling of the IDE interrupt
Input data FIFO triggering number
Exchanging of output data channels
Output data endian
Enabling/disabling of the ODF interrupt
Output data FIFO triggering number
Register Bit
Items to be Set
Start initial setting
Set necessary parameters.
Set the SRCEN bit in SRCCTRL to 1
Initial setting completed
Enabling/disabling of the CEF interrupt
Figure 28.2 Sample Flowchart for Initial Setting