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Section 12 Compare Match Timer
R01UH0134EJ0400 Rev. 4.00 Page 655 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
12.3 Operation
12.3.1 Interval Count Operation
When an internal clock is selected with the CKS[1:0] bits in CMCSR and the STR bit in CMSTR
is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and
CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the
CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested.
CMCNT then starts counting up again from H'0000.
Figure 12.2 shows the operation of the compare match counter.
CMCOR
H'0000
CMCNT value
Time
Counter cleared by compare
match with CMCOR
Figure 12.2 Counter Operation
12.3.2 CMCNT Count Timing
One of four clocks (P/8, P/32, P/128, and P/512) obtained by dividing the peripheral clock
(P) can be selected with the CKS1 and CKS0 bits in CMCSR. Figure 12.3 shows the timing.
CMCNT
N N + 1
Peripheral clock
(Pφ)
Clock
N
Clock
N + 1
Internal clock
Count clock
Figure 12.3 Count Timing