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Section 2 CPU
Page 88 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Instruction Instruction Code Operation
Execu-
tion
Cycles T Bit
Compatibility
SH2E SH4
SH-2A/
SH2A-
FPU
FMOV.S @(R0, Rm), FRn 1111nnnnmmmm0110 (R0 + Rm) FRn 1 Yes Yes Yes
FMOV.D @(R0, Rm), DRn 1111nnn0mmmm0110 (R0 + Rm) DRn 2 Yes Yes
FMOV.S @Rm+, FRn 1111nnnnmmmm1001 (Rm) FRn, Rm+=4 1 Yes Yes Yes
FMOV.D @Rm+, DRn 1111nnn0mmmm1001 (Rm) DRn, Rm += 8 2 Yes Yes
FMOV.S @Rm, FRn 1111nnnnmmmm1000 (Rm) FRn 1 Yes Yes Yes
FMOV.D @Rm, DRn 1111nnn0mmmm1000 (Rm) DRn 2 Yes Yes
FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001
0111dddddddddddd
(disp 4 + Rm) FRn 1 Yes
FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001
0111dddddddddddd
(disp 8 + Rm) DRn 2 Yes
FMOV.S FRm, @(R0,Rn) 1111nnnnmmmm0111 FRm (R0 + Rn) 1 Yes Yes Yes
FMOV.D DRm, @(R0,Rn) 1111nnnnmmm00111 DRm (R0 + Rn) 2 Yes Yes
FMOV.S FRm, @-Rn 1111nnnnmmmm1011 Rn-=4, FRm (Rn) 1 Yes Yes Yes
FMOV.D DRm, @-Rn 1111nnnnmmm01011 Rn-=8, DRm (Rn) 2 Yes Yes
FMOV.S FRm, @Rn 1111nnnnmmmm1010 FRm (Rn) 1 Yes Yes Yes
FMOV.D DRm, @Rn 1111nnnnmmm01010 DRm (Rn) 2 Yes Yes
FMOV.S FRm,
@(disp12,Rn)
0011nnnnmmmm0001
0011dddddddddddd
FRm (disp 4 + Rn) 1 Yes
FMOV.D DRm,
@(disp12,Rn)
0011nnnnmmm00001
0011dddddddddddd
DRm (disp 8 + Rn) 2 Yes
FMUL FRm, FRn 1111nnnnmmmm0010 FRn FRm FRn 1 Yes Yes Yes
FMUL DRm, DRn 1111nnn0mmm00010 DRn DRm DRn 6 Yes Yes
FNEG FRn 1111nnnn01001101 -FRn FRn 1 Yes Yes Yes
FNEG DRn 1111nnn001001101 -DRn DRn 1 Yes Yes
FSCHG 1111001111111101 FPSCR.SZ=~FPSCR.S
Z
1 Yes Yes
FSQRT FRn 1111nnnn01101101 FRn FRn 9 Yes Yes
FSQRT DRn 1111nnn001101101 DRn DRn 22 Yes Yes
FSTS FPUL,FRn 1111nnnn00001101 FPUL FRn 1 Yes Yes Yes
FSUB FRm, FRn 1111nnnnmmmm0001 FRn-FRm FRn 1 Yes Yes Yes