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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1431 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
13 to 11 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
10 BFRE 0 R/W BRDY Interrupt Operation Specification
Specifies the BRDY interrupt generation timing from
this module to the CPU with respect to the selected
pipe.
0: BRDY interrupt upon transmitting or receiving of
data
1: BRDY interrupt upon completion of reading of
data
This bit is valid when any of pipes 1 to 5 is selected.
When this bit has been set to 1 and the selected pipe
is in the receiving direction, this module detects the
transfer completion and generates the BRDY
interrupt on having read the pertinent packet.
When the BRDY interrupt is generated with the
above conditions, 1 needs to be written to BCLR.
The FIFO buffer assigned to the selected pipe is not
enabled for reception until 1 is written to BCLR.
When this bit has been set to 1 and the selected pipe
is in the transmitting direction, this module does not
generate the BRDY interrupt.
For details, refer to section 26.4.2 (1), BRDY
Interrupt.
Modify these bits while CSSTS is 0 and PID is NAK
and before the pipe is selected by the CURPIPE bits.
To modify these bits after completing USB
communication using the selected pipe, write 1 and
then 0 to ACLRM continuously to clear the FIFO
buffer assigned to the selected pipe while the
CSSTS, PID, and CURPIPE bits are in the above-
described state.
Before modifying these bits after modifying the PID
bits for the selected pipe from BUF to NAK, check
that CSSTS and PBUSY are 0. However, if the PID
bits have been modified to NAK by this module,
checking PBUSY is not necessary.