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Section 10 Direct Memory Access Controller
Page 398 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
10.3.8 DMA Operation Register (DMAOR)
The DMA operation register (DMAOR) is a 16-bit readable/writable register that specifies the
priority level of channels at the DMA transfer. This register also shows the DMA transfer status.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
R R R/W R/W R R R/W R/W R R R R R R/(W)*R/(W)* R/W
Note: Only 0 can be written to clear the flag after 1 is read.*
Bit:
Initial value:
R/W:
- - CMS[1:0] - - PR[1:0] - - - - - AE NMIF DME
Bit Bit Name
Initial
Value
R/W Description
15, 14 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
13, 12 CMS[1:0] 00 R/W Cycle Steal Mode Select
These bits select either normal mode or intermittent
mode in cycle steal mode.
It is necessary that the bus modes of all channels be
set to cycle steal mode to make the intermittent mode
valid.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
Executes one DMA transfer for every 16 cycles of
B clock.
11: Intermittent mode 64
Executes one DMA transfer for every 64 cycles of
B clock.
11, 10 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.