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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 429 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
CKIO
Address
RD
Data
WEn
WAIT
CS
T1 T2 Taw T1 T2
DACKn
(Active low)
TEND
(Active low)
Note:
TEND is asserted for the last unit of DMA transfer. If a transfer unit
is divided into multiple bus cycles and the CS is negated between
the bus cycles, TEND is also divided.
Figure 10.16 Bus State Controller Normal Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)