Filter
Top Products
Section 18 Serial Sound Interface
Page 916 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
0 RDF 0 R/(W)* Receive Data Full
Indicates that, when the FIFO is operating for reception,
the received data is transferred to the receive FIFO
data register (SSIFRDR) and the number of data bytes
in the FIFO data register has become greater than the
receive trigger number specified by RTRG[1:0] in the
FIFO control register (SSIFCR).
0: Number of received data bytes in SSIFRDR is less
than the set receive trigger number.
[Clearing conditions]
Power-on reset
0 is written to RDF after the receive FIFO is empty
with writing 1 to RFRST.
0 is written to RDF after data is read from SSIFRDR
until the number of data bytes in SSIFRDR
becomes less than the set receive trigger number.
The direct memory access controller is activated by
receive data full (RXI) interrupt, and data is read
from SSIFRDR until the number of data bytes in
SSIFRDR becomes less than the set receive trigger
number.
1: Number of received data bytes in SSIFRDR is equal
to or greater than the set receive trigger number.
[Setting condition]
Data of the number of bytes that is equal to or
greater than the set receive trigger number is stored
in SSIFRDR.*
1
Note: 1. Since SSIFRDR is an 8-stage FIFO register,
the amount of data that can be read from it
while RDF = 1 is the set receive trigger number
of bytes at maximum.
Continuing to read data from SSIFRDR after
reading all the data will result in undefined data
to be read. The number of data bytes in
SSIFRDR is indicated in the RDC bits in
SSIFSR.
Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored.