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Section 26 USB 2.0 Host/Function Module
Page 1362 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
26.3.5 Test Mode Register (TESTMODE)
TESTMODE is a register that controls the USB test signal output during high-speed operation.
This register is initialized by a power-on reset.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit:
Initial value:
R/W:
0000000100000000
R R R R R R R R R R R R R/W R/W R/W R/W
———————————— UTST[3:0]
Bit Bit Name
Initial
Value R/W Description
15 to 9 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
8 1 R Reserved
This bit is always read as 1. The write value should
always be 1.
7 to 4 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
3 to 0 UTST[3:0] 0000 R/W Test Mode
This module outputs the USB test signals during the
high-speed operation, when these bits are written
appropriate value.
Table 26.6 shows test mode operation of this
module.