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Section 18 Serial Sound Interface
R01UH0134EJ0400 Rev. 4.00 Page 903 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
9 PDTA 0 R/W Parallel Data Alignment
When the data word length is 32 bits, this configuration
field has no meaning.
This bit applies to SSIRDR in receive mode and
SSITDR in transmit mode.
When data word length is 8 or 16 bits:
0: The lower bits of parallel data (SSITDR, SSIRDR)
are transferred prior to the upper bits.
1: The upper bits of parallel data (SSITDR, SSIRDR)
are transferred prior to the lower bits.
When data word length is 18, 20, 22, or 24 bits:
0: Parallel data (SSITDR, SSIRDR) is left-aligned.
1: Parallel data (SSITDR, SSIRDR) is right-aligned.
PDTA = 0
DWL[2:0] SSITDR/SSIRDR[31:0]
000
31 24 23 16 15 8 7
0
4th word 3rd word 2nd word
1st word
001
31 1615
0
2nd word
1st word
010
31 14 13
0
Valid
Invalid
011
31 12 11
0
Valid
Invalid
100
31 109
0
Valid
Invalid
101
31 8 7
0
Valid
Invalid
110
31 0
Valid