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Section 11 Multi-Function Timer Pulse Unit 2
Page 560 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(k) Complementary PWM Mode 0 and 100% Duty Output
In complementary PWM mode, 0 and 100 duty cycles can be output as required. Figures
11.49 to 11.53 show output examples.
100 duty output is performed when the compare register value is set to H'0000. The waveform in
this case has a positive phase with a 100 on-state. 0 duty output is performed when the
compare register value is set to the same value as TGRA_3. The waveform in this case has a
positive phase with a 100 off-state.
On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off
compare-match for the same phase occur simultaneously, both compare-matches are ignored and
the waveform does not change.
(l) Toggle Output Synchronized with PWM Cycle
In complementary PWM mode, toggle output can be performed in synchronization with the PWM
carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example
of a toggle output waveform is shown in figure 11.54.
This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match
between TCNT4 and H'0000.
The output pin for this toggle output is the TIOC3A pin. The initial output is 1.
TGRA_3
H'0000
Toggle output
TIOC3A pin
TCNT_4
TCNT_3
Figure 11.54 Example of Toggle Output Waveform Synchronized with PWM Output