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Section 5 Clock Pulse Generator
Page 116 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Figure 5.1 shows a block diagram of the clock pulse generator.
x 1
x 1/2
x 1/3
x 1/4
x 1/6
x 1/8
x 1/12
On-chip oscillator circuit
PLL circuit
(x8, x12)
x 1/1
x 1/3
x 1/4
CPU clock
(Iφ Max: 144 MHz)
Peripheral clock
(Pφ Max: 36 MHz)
Bus clock
(Bφ = CKIO Max: 72 MHz)
CKIO
Control unit
Standby control circuit
Clock frequency
control circuit
Bus interface
Peripheral bus
FRQCR
[Legend]
FRQCR: Frequency control register
Crystal
oscillator
Crystal
oscillator
XTAL
EXTAL
USB_X2
USB_X1
MD_CLK1
MD_CLK0
Divider 1
Divider 2
Figure 5.1 Block Diagram