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Section 2 CPU
Page 66 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Instruction Formats
Source
Operand
Destination
Operand
Example
m format
xxxx
mmmmxxxx xxxx
15 0
mmmm: Register
direct
Control register or
system register
LDC Rm,SR
mmmm: Register
indirect with post-
increment
Control register or
system register
LDC.L @Rm+,SR
mmmm: Register
indirect
JMP @Rm
mmmm: Register
indirect with pre-
decrement
R0 (Register direct) MOV.L @-Rm,R0
mmmm: PC relative
using Rm
BRAF Rm
nm format
nnnn
xxxx xxxx
15 0
mmmm
mmmm: Register
direct
nnnn: Register
direct
ADD Rm,Rn
mmmm: Register
direct
nnnn: Register
indirect
MOV.L Rm,@Rn
mmmm: Register
indirect with post-
increment (multiply-
and-accumulate)
nnnn*: Register
indirect with post-
increment (multiply-
and-accumulate)
MACH, MACL MAC.W @Rm+,@Rn+
mmmm: Register
indirect with post-
increment
nnnn: Register
direct
MOV.L @Rm+,Rn
mmmm: Register
direct
nnnn: Register
indirect with pre-
decrement
MOV.L Rm,@-Rn
mmmm: Register
direct
nnnn: Indexed
register indirect
MOV.L
Rm,@(R0,Rn)
md format
xxxx dddd
15 0
mmmm
xxxx
mmmmdddd:
Register indirect
with displacement
R0 (Register direct) MOV.B
@(disp,Rm),R0