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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 321 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(6) Single Write
A write access ends in one cycle when data is written in a cache-disabled space and the data bus
width is larger than or equal to access size. As a single write or burst write with burst length 1 is
set in SDRAM, only the required data is output. The write access that ends in one cycle is called
single write. Figure 9.19 shows the single write basic timing.
TapTr Tc1 Trwl
CKIO
A25 to A0
CSn
RD/WR
RAS
DQMx
D15 to D0
BS
DACKn*
2
A12/A11*
1
CAS
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.19 Single Write Basic Timing (Auto-Precharge)