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Section 17 I
2
C Bus Interface 3
Page 868 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
17.4 Operation
The I
2
C bus interface 3 can communicate either in I
2
C bus mode or clocked synchronous serial
mode by setting FS in SAR.
17.4.1 I
2
C Bus Format
Figure 17.3 shows the I
2
C bus formats. Figure 17.4 shows the I
2
C bus timing. The first frame
following a start condition always consists of eight bits.
SASLA
7n
R/W DATA A
1
1m
111
A/A
1
P
1
S SLA
7n1 7
R/W A DATA
11
1m1
1
A/A
1
S
1
SLA R/W
1
1m2
A
1
DATA
n2
A/A
1
P
1
(a) I
2
C bus format (FS = 0)
(b) I
2
C bus format (Start condition retransmission, FS = 0)
n: Transfer bit count (n = 1 to 8)
m: Transfer frame count (m ≥ 1)
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
Figure 17.3 I
2
C Bus Formats
SDA
SCL
S SLA R/W A
981-7 981-7 981-7
DATA A DATA A
P
Figure 17.4 I
2
C Bus Timing
[Legend]
S: Start condition. The master device drives SDA from high to low while SCL is high.
SLA: Slave address
R/W: Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
A: Acknowledge. The receive device drives SDA to low.
DATA: Transfer data
P: Stop condition. The master device drives SDA from low to high while SCL is high.