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Page 2096 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
Item Page Revision (See Manual for Details)
37.4.11 Serial I/O with FIFO
Timing
Figure 37.58 Transmission
and Reception Timing (Slave
Mode 1)
2028 Figure amended
SCK_SIO (input)
t
STDD
t
FSH
t
FSS
SIOFSYNC (input)
TXD_SIO
37.4.15 Video Display
Controller 3 Timing
Table 37.21 Video Display
Controller 3 Timing
2038 Table amended
erugiF tinU .xaM .pyT .niM lobmyS metI
DV_CLK input clock
frequency
t
cyc
⎯ 27 ⎯ MHz Figure 37.71
DV_CLK input clock low
pulse width
t
WIL
0.4 ⎯ ⎯ t
cyc
DV_CLK input clock high
pulse width
t
WIH
0.4 ⎯ ⎯
LCD_EXTCLK input clock
frequency
t
cyc
⎯ ⎯ 36 MHz
LCD_EXTCLK input clock
low pulse width
t
WIL
0.4 ⎯ ⎯ t
cyc
LCD_EXTCLK input clock
high pulse width
t
WIH
0.4 ⎯ ⎯
LCD_CLK output clock
frequency
t
cyc
⎯ ⎯ 36 MHz Figure 37.72
38.1 Pin States
Table 38.1 Pin States
2047 Table amended
etatS niP noitcnuF niP
Type Pin Name
Normal State
(Other than
States at
Right)
Power-On
Reset*
1
Pin State Retained*
2
Power-Down State
Bus
Mastership
Release
EBUSKEEPE*
3
(Other
than States at Right)
Power-On
Reset*
4
Deep
Standby
Mode
Software
Standby
Mode
0 1
Clock EXTAL*
6
Clock
operation
mode
Z/I I I I 2 ,0 *
5
I I
Z Z Z Z Z Z 3 ,1
XTAL*
6
L/O O O O *
5
O/L*
5
O
CKIO Boot
mode
0 O/Z*
7
O O O/Z*
7
O/Z*
7
O/Z*
7
O/Z*
7
Other O/Z*
7
O O/Z*
7
Z/O *
7
O/Z*
7
O/Z*
7