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Section 9 Bus State Controller
Page 246 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
11 ENDIAN 0 R/W Endian Setting
Specifies the arrangement of data in a space.
0: Arranged in big endian
1: Arranged in little endian
Note: Little endian cannot be set for area 0 in boot
mode 0. In this case, this bit of CS0BCR is
always read as 0. The write value should
always be 0.
10, 9 BSZ[1:0] 10 R/W Data Bus Width Specification
Specify the data bus widths of spaces.
00: Reserved (setting prohibited)
01: 8-bit size
10: 16-bit size
11: Bus width selected by address when the MPX-I/O
is used. When the MPX-I/O is not used, setting
prohibited.
For MPX-I/O, selects bus width by address
Notes: 1. If area 5 is specified as MPX-I/O, the bus
width can be specified as 8 bits or 16 bits
by the address according to the SZSEL
bit in CS5WCR by specifying the
BSZ[1:0] bits to 11. The fixed bus width
can be specified as 8 bits or 16 bits
2. In boot mode 0, the BSZ[1:0] bits
settings in CS0BCR are ignored.
3. If area 5 or area 6 is specified as
PCMCIA space, the bus width can be
specified as either 8 bits or 16 bits.
4. If area 2 or area 3 is specified as
SDRAM space, the bus width can be
specified as 16 bits.
5. If area 0 is specified as clocked
synchronous burst ROM space, the bus
width can be specified as 16 bits.