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Section 27 Video Display Controller 3
R01UH0134EJ0400 Rev. 4.00 Page 1619 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.35 Horizontal Sync Signal Timing Control Register (PANEL_HSYNC_TIM)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
151413121110987654321
0
0000000000000000
RRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
0000000000001010
RRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
----- HSYNC_START[10:0]
- - - - - HSYNC_END[10:0]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 27 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
26 to 16 HSYNC_START
[10:0]
H'000 R/W These bits specify in number of panel clock cycles
the interval between the reference horizontal sync
signal and the point where the horizontal sync
signal (HSYNC) for panel is set to 1.
15 to 11 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
10 to 0 HSYNC_END
[10:0]
H'00A R/W These bits specify in number of panel clock cycles
the interval between the reference horizontal sync
signal and the point where the horizontal sync
signal (HSYNC) for panel is cleared to 0.
Note: Be sure to satisfy HSYNC_START HSYNC_END; otherwise, correct operation is not
guaranteed.