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Section 23 CD-ROM Decoder
Page 1234 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
2 ST_BLKLM 0 R/W ISY interrupt ST_BLKL (bit 2 in the CROMST0 register)
source mask
1 ST_
SECSM
0 R/W ISY interrupt ST_SECS (bit 1 in the CROMST0 register)
source mask
0 ST_
SECLM
0 R/W ISY interrupt ST_SECL (bit 0 in the CROMST0 register)
source mask
23.3.46 CD-ROM Decoder Reset Control Register (ROMDECRST)
The CD-ROM decoder reset control register (ROMDECRST) resets the random logic of the CD-
ROM decoder and clears the RAM in the CD-ROM decoder.
76543210
00000000
R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
LOGI
CRST
RAM
RST
------
Bit Bit Name
Initial
Value
R/W Description
7 LOGICRST 0 R/W CD-ROM Decoder Random Logic Reset Signal
A reset signal is output while this bit is set to 1.
6 RAMRST 0 R/W CD-ROM Decoder RAM Clearing Signal
Refer to the RAMCLRST bit in the RSTSTAT register to
confirm that RAM clearing is complete.
5 to 0 All 0 R/W Reserved
These bits are always read as 0.The write value should
always be 0.
Note: Before setting LOGICRST to 1, make sure that the RAMRST bit is cleared to 0 and then
write B'10000000 to this register.