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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 423 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
DREQ
CPU CPUBus cycle CPU DMA DMA CPU CPU DMA DMA CPU
Read/Write Read/Write
More than 16 or 64 Bφ clock cycles
(depending on the state of bus used by bus master such as CPU)
Figure 10.8 Example of DMA Transfer in Cycle-Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)
(b) Burst Mode
In burst mode, once this module obtains the bus mastership, it does not release the bus mastership
and continues to perform transfer until the transfer end condition is satisfied. In external request
mode with low-level detection of the DREQ pin, however, when the DREQ pin is driven high, the
bus mastership is passed to another bus master after the DMA transfer request that has already
been accepted ends, even if the transfer end conditions have not been satisfied.
Figure 10.9 shows DMA transfer timing in burst mode.
CPU CPU CPU DMA DMA DMA DMA CPU
DREQ
Bus cycle
Read ReadWrite
Write
CPU
Figure 10.9 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)