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R01UH0134EJ0400 Rev. 4.00 Page xxxi of xl
Sep 24, 2014
25.3.12 Control Code FIFO Register (FLECFIFO) ..................................................... 1314
25.3.13 Transfer Control Register (FLTRCR) ............................................................. 1315
25.3.14 Bus Hold Time Setting Register (FLHOLDCR) ............................................. 1316
25.3.15 4-Symbol ECC Processing Result Register n (FL4ECCRESn) (n = 1 to 4) ... 1317
25.3.16 4-Symbol ECC Control Register (FL4ECCCR) ............................................. 1318
25.3.17 4-Symbol ECC Error Count Register (FL4ECCCNT) .................................... 1320
25.4 Operation ........................................................................................................................ 1322
25.4.1 Access Sequence ............................................................................................. 1322
25.4.2 Operating Modes ............................................................................................. 1322
25.4.3 Register Setting Procedure .............................................................................. 1323
25.4.4 Command Access Mode ................................................................................. 1324
25.4.5 Sector Access Mode ........................................................................................ 1327
25.4.6 ECC Error Correction ..................................................................................... 1332
25.4.7 Status Read ..................................................................................................... 1337
25.5 Interrupt Sources ............................................................................................................. 1338
25.6 DMA Transfer Specifications ......................................................................................... 1338
25.7 Usage Notes .................................................................................................................... 1339
25.7.1 External Bus Mastership Release Timing ....................................................... 1339
25.7.2 Writing to the Control-Code Area when 4-Symbol ECC Circuit is in Use ..... 1341
25.7.3 Usage Notes for the SNAND Bit .................................................................... 1342
Section 26 USB 2.0 Host/Function Module .................................................... 1343
26.1 Features ........................................................................................................................... 1343
26.2 Input/Output Pins ............................................................................................................ 1345
26.3 Register Description ....................................................................................................... 1347
26.3.1 System Configuration Control Register (SYSCFG) ....................................... 1350
26.3.2 CPU Bus Wait Setting Register (BUSWAIT) ................................................ 1354
26.3.3 System Configuration Status Register (SYSSTS) ........................................... 1355
26.3.4 Device State Control Register (DVSTCTR) ................................................... 1356
26.3.5 Test Mode Register (TESTMODE) ................................................................ 1362
26.3.6 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG) .............. 1365
26.3.7 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO)........................................... 1366
26.3.8 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL) ........... 1368
26.3.9 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR) ...... 1376
26.3.10 Interrupt Enable Register 0 (INTENB0) ......................................................... 1380
26.3.11 Interrupt Enable Register 1 (INTENB1) ......................................................... 1382
26.3.12 BRDY Interrupt Enable Register (BRDYENB) ............................................. 1384
26.3.13 NRDY Interrupt Enable Register (NRDYENB) ............................................. 1385
26.3.14 BEMP Interrupt Enable Register (BEMPENB) .............................................. 1387
26.3.15 SOF Output Configuration Register (SOFCFG) ............................................. 1388