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Section 19 Serial I/O with FIFO
Page 940 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Figure 19.1 shows a block diagram.
Timing
control
Control
registers
Baud rate
generator
P/S
S/P
Transmit
FIFO
(32 bits x16
stages)
Receive
FIFO
(32 bits x16
stages)
Bus interface
Peripheral bus
1/nMCLK
SIOFSCK
SIOFSYNC
SIOFTxD
SIOFRxD
Interrupt
request
AUDIO_CLK
AUDIO_X1
Figure 19.1 Block Diagram