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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 253 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
CS2WCR, CS3WCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
RRRRRRRRRRRR/WRRRR
0000010100000000
R R R R R R/W R/W R/W R/W R/W R R R R R R
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
-----------BAS----
----- WR[3:0] WM - - - - - -
Bit Bit Name
Initial
Value
R/W Description
31 to 21 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
20 BAS 0 R/W SRAM with Byte Selection Byte Access Select
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read access
cycle and asserts the RD/WR signal at the write
timing.
19 to 11 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.