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R01UH0134EJ0400 Rev. 4.00 Page 2073 of 2108
Sep 24, 2014
Item Page Revision (See Manual for Details)
15.4.1 Overview 747 Description amended
For serial communication, this module has an
asynchronous mode in which characters are synchronized
individually, and a clock synchronous mode in which
communication is synchronized with clock pulses. Note that
on the SH7262 channels other than 0 to 2, and on the
SH7264 channels other than 0 to 3, cannot be set to clock
synchronous mode.
This module has a 16-stage FIFO buffer for both
transmission and receptions, reducing the overhead of the
CPU, and enabling continuous high-speed communication.
Furthermore, channel 1 on the SH7262, and channels 1
and 3 on the SH7264, have RTS and CTS signals to be
used as modem control signals.
(2) Clock Synchronous
Mode (SH7262: Channels 0
to 2, SH7264: Channels 0 to
3)
748 Title amended
15.4.2 Operation in
Asynchronous Mode
(3) Transmitting and
Receiving Data
756 Description amended
4. When modem control is enabled in channel 1 on the
SH7262, and channels 1 and 3 on the SH7264,
transmission can be stopped and restarted in
accordance with the CTS input value.
16.3 Register Descriptions
Table 16.2 Register
Configuration
779,
780
Table amended
Channel Register Name Abbreviation*
1
R/W
Initial
Value Address
Access
Size
0 Control register_0 SPCR_0 R/W H'00 H'FFFF8000 8, 16
Buffer data count setting
register_0
SPBFDR_0 R H'0000 H'FFFF8022 16
Data register_1
Buffer data count setting
register_1
SPBFDR_1 R H'0000 H'FFFF8822 8, 16
1 Control register_1 SPCR_1 R/W H'00 H'FFFF8800 8, 16
SPDR_1 R/W Undefined H'FFFF8804 8, 16,
32
16.3.8 Bit Rate Register
(SPBR)
Table 16.3 Relationship
between SPBR and BRDV1
and BRDV0 Settings
794 Table amended
SPBR (n) BRDV[1:0] (N) Division Ratio
Bit Rate
Bφ = 40 MHz Bφ = 48 MHz Bφ = 72 MHz
5 0 12 3.33 Mbps 4.00 Mbps 6.0 Mbps