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Section 20 Controller Area Network
Page 1078 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
20.6 DMAC Interface
The DMAC can be activated by the reception of a message in mailbox 0. When DMAC transfer
ends after DMAC activation has been set, flags of RXPR0 and RFPR0 are cleared automatically.
An interrupt request due to a receive interrupt from this module cannot be sent to the CPU in this
case. Figure 20.26 shows a DMAC transfer flowchart.
DMAC initialization
DMAC enable register setting
DMAC register information setting
End of DMAC transfer?
RXPR and RFPR flags clearing
Yes
END
Message reception in RCAN-TL1
mailbox 0
Interrupt to CPU
DMAC interrupt
enabled?
Yes
DMAC activation
: Settings by user
: Processing by hardware
No
No
Figure 20.26 DMAC Transfer Flowchart