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Section 12 Compare Match Timer
Page 660 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
12.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the writing has
priority over the count-up. In this case, the count-up is not performed. The byte data on the other
side, which is not written to, is also not counted and the previous contents are retained.
Figure 12.7 shows the timing when the count-up occurs in the T2 cycle while writing to
CMCNTH in bytes.
CMCNTH
T1 T2
CMCNTH
MN
CMCNTL
XX
Peripheral clock
(Pφ)
Address signal
Internal write signal
CMCNT count-up
enable signal
CMCSR write cycle
Figure 12.7 Conflict between Byte-Write and Count-Up Processes of CMCNT
12.5.4 Compare Match between CMCNT and CMCOR
Do not set the same value in CMCNT and CMCOR while CMCNT is not counting.