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Section 19 Serial I/O with FIFO
Page 976 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(2) Regarding Transmit and Receive Classification
The transmit request and receive request are signals indicating the state; after being set, if the state
of the transmit/receive FIFO change, they are automatically cleared by this module.
When the DMA transfer is used, the signal is cleared to 0 by the direct memory access controller.
If the setting condition is still satisfied after the access using the direct memory access controller,
it is set to 1 again.
(3) Processing when Errors Occur
On occurrence of each of the errors indicated as a status in SISTR, this module performs the
following operations.
Transmit FIFO underflow (TFUDF)
The immediately preceding transmit data is again transmitted.
Transmit FIFO overflow (TFOVF)
The contents of the transmit FIFO are protected, and the write operation causing the overflow
is ignored.
Receive FIFO overflow (RFOVF)
Data causing the overflow is discarded and lost.
Receive FIFO underflow (RFUDF)
The read value is undefined.
FS error (FSERR)
The internal counter is reset according to the sync signal in which an error occurs.