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Section 25 NAND Flash Memory Controller
Page 1328 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Figure 25.10 shows the relationship of DMA transfer between sectors in flash memory (data and
control code) and memory on the address space.
Data (512 bytes)
Flash memory
Control
code
(16 bytes)
This module
FLDT FIFO
FLEC FIFO
DMA (channel 0)
transfer
DMA (channel 1)
transfer
Address area
Data area
Control code area
Figure 25.10 Relationship between DMA Transfer and Sector (Data and Control Code),
and Memory and DMA Transfer