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Section 32 General Purpose I/O Ports
R01UH0134EJ0400 Rev. 4.00 Page 1749 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(2) Port G Data Register 0 (PGDR0)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PG15
DR
PG14
DR
PG13
DR
PG12
DR
PG11
DR
PG10
DR
PG9
DR
PG8
DR
PG7
DR
PG6
DR
PG5
DR
PG4
DR
PG3
DR
PG2
DR
PG1
DR
PG0
DR
Bit:
Initial value:
R/W:
Bit Bit Name Initial Value R/W Description
15 PG15DR 0 R/W See table 32.19
14 PG14DR 0 R/W
13 PG13DR 0 R/W
12 PG12DR 0 R/W
11 PG11DR 0 R/W
10 PG10DR 0 R/W
9 PG9DR 0 R/W
8 PG8DR 0 R/W
7 PG7DR 0 R/W
6 PG6DR 0 R/W
5 PG5DR 0 R/W
4 PG4DR 0 R/W
3 PG3DR 0 R/W
2 PG2DR 0 R/W
1 PG1DR 0 R/W
0 PG0DR 0 R/W
Table 32.19 Port G Data Registers 1, 0 (PGDR1, PGDR0) Read/Write Operation
Bits 8 to 0 of PGDR1 and Bits 15 to 0 of PGDR0
PGIOR1, 0 Pin Function Read Operation Write Operation
0 General input Pin state Can write to PGDR0/PGDR1, but it has no effect
on the pin state
Other than
general input
Pin state Can write to PGDR0/PGDR1, but it has no effect
on the pin state
1 General output PGDR0/PGDR1
value
Value written is output to pin
Other than
general output
PGDR0/PGDR1
value
Can write to PGDR0/PGDR1, but it has no effect
on the pin state