Filter
Top Products
Section 17 I
2
C Bus Interface 3
Page 870 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
TDRE
TEND
ICDRT
ICDRS
12 123456789
A
R/W
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
[5] Write data to ICDRT (third byte)
[2] Instruction of start
condition issuance
[3] Write data to ICDRT (first byte)
[4] Write data to ICDRT (second byte)
User
processing
Bit 7
Slave address
Address + R/W
Data 1
Data 1
Data 2
Address + R/W
Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 17.5 Master Transmit Mode Operation Timing (1)
TDRE
TEND
ICDRT
ICDRS
19 23456789
A
A/A
[6] Issue stop condition. Clear TEND.
[7] Set slave receive mode
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
Bit 7 Bit 6
Data n
Data n
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[5] Write data to ICDRT
User
processing
Figure 17.6 Master Transmit Mode Operation Timing (2)